Instructor: Bob Rinker Office: JEB 324 Email: rinker@cs.uidaho.edu Phone: (208)885-7378 (direct line) Office Hours (Fall 2023):
TBD
Catalog Description:
CS J451/J551 Advanced Computer Architecture (3 cr). Same as ECE J441/J541.
Principles and alternatives in instruction set design; processor implementation techniques, pipelining,
parallel processors, memory hierarchy, and input/output; measurement of performance and cost/performance
trade-off. Additional work required for graduate credit.
Prereq: CS 150, Stat 301 or Permission Syllabus: Downloadable from
here.
Grading:
Your grade will be calculated using the following percentages:
CS551/ECE541
CS451/ECE441
Two mid-semester exams
40%
50%
Final exam (comprehensive)
20%
25%
Assignments
20%
25%
Term Project
20%
Total
100%
100%
The letter grade you receive from the course will be determined as follows:
90%-100%
A
89.9%-80%
B
79.9%-70%
C
69.9%-60%
D
Below 60%
F
The instructor reserves the right to adjust these percentages lower if
deemed necessary.
Announcements:
Welcome to the class! Any announcements will show up here as needed.
Due to the lack of natural gas in Moscow, the UI main campus is closed. Since most of the people in the class signed up for the in-class sections, we have been asked to cancel class. I realize that many (most?) of you at least occasionally attend via zoom, but I will honor the request to cancel class. We will definitely meet on monday, regardless of the situation at that time.
Please stay warm! Enjoy!
- Bob
Assignments:
Assignments will show up here sometime after they are assigned.
Assignment 1 -
here
Due: September 11
Assignment 2 -
here
Due: September 18
Assignment 3 -
here
Due: October 2
`
A blank Tomasulo worksheet is available here
(
pdf
)
Assignment 4 -
here
Due: October 23
Assignment 5 -
here
Due: October 30
Assignment 6 -
here
Due: November 10
Graduate Student Project Info
here
The source code for the program (slightly modified from the version in the text)
is available
here (ctrl-click to download)
Lecture slides
Computer History slides
(pdf)
Chapter 1 slides
(pdf)
Appendix A slides
(pdf)
Appendix C slides
(pdf)
Chapter 3 slides
(pdf)
Appendix B slides on caches
(pdf)
Appendix B slides on Virtual memory
(pdf)
Chapter 4 slides
(pdf)
Chapter 5 slides
(pdf)
Chapter 5 synchronization slides
(pdf)
Appendix D slides on Storage Systems
(pdf)
Appendix D introduction to queuing theory
(pdf)
Appendix D More queuing theory
(pdf)
Queue Formula Handouts (from Jain, 1991):
M/M/1 Queue
M/M/m Queue
Moore's Law paper (reference from the Wikipedia page)
(pdf)
Papers on Simultaneous Multithreading
here
MIPS Programming card
(ps or
pdf)
More detailed MIPS info
(ps or
pdf)