A reconfigurable data processor architecture has been designed and implemented at UI, with the goal to achieve data high throughput with low power consumption for spacecraft instrumentation and control. The architecture has been validated on a set of challenge algorithms. A prototype chip was fabricated and tested, yielding impressive computation to power ratios. This presentation will describe the chip, with a focus on the set of software tools that was was developed to facilitate programming and simulating the architecture.
The talk is based on a journal paper that submitted to the IEEE TVLSI.