Advances in reconfigurable computing machinery (RCM) have provoked a blurring of the boundary between hardware and software. The field-programmable gate array (FPGA) has contributed to this blurring by providing a programmable IC fabric capable of achieving substantial performance increases over general-purpose processors (GPPs).
It is sometimes the case, however, that the highly concurrent, spatial computational capabilities of the FPGA are configured to behave as a sequential, synchronous GPP. In this presentation we describe an investigation into creating a model and method for automating the transformation of programs targeted for GPPs into synthesizable machine descriptions capable of leveraging the spatial computational capability of the FPGA.
We show how such descriptions can be used as an alternative to configuring an FPGA to behave as a GPP, and discuss situations where it may be desirable to do so. We then describe a prototype that transforms programs targeted for the Intel 8051 into synthesizable special-purpose machine descriptions, and present results comparing the area and maximum operating frequency of these generated descriptions with the area and maximum operating frequency of an existing Intel 8051 soft processor implementation. Our preliminary findings indicate that for some 8051 programs this prototype generates a custom machine description that, when synthesized, consumes less area and is capable of operating at a higher maximum frequency than the existing 8051 soft processor when hosting the same program.