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Sponsor: Troy Pearse, Hewlett-Packard, Boise,
ID
208-396-4557 Troy_Pearse@hp.com
Project Description: The APIDoc project is an HTML-based documentation system (similar to Java's javadoc) for IDL (Interface Definition Language) files. These files define programming structures used at Hewlett Packard's printer division in Boise, Idaho. APIDoc works with an existing HP tool, APIHeader, that generates comment structures within the IDL files. APIHeader enforces certain standard in commenting and APIDoc extracts these comment structures and creates navigable guides viewable in web browsers.
The original APIDoc project (version 1.0) was created by a senior design team in Spring, 2001. The goal of this semester's (Fall, 2001) team is to greatly enhance the current project. APIDoc is currently used by professional programmers and it is our goal to ensure that each release of the software is fully functional and backwards-compatible with previous versions.
Link to Spring 2000-2001 project.
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Sponsor: Bob Rinker, University of Idaho,
Computer Science Dept.
885-7378 rinker@cs.uidaho.edu
Project Description: The
Cameron Project is a DARPA funded project named after a mountain pass in
Colorado. Like a mountain pass, its function is to provide a simple and
effective path between two otherwise separate areas. In this case hardware and
software. It is designed to allow a programmer to write high level code that can
be compiled straight into hardware. To do this, the project researchers
developed a new language called SA-C, Single Assignment C (pronounced
"sassy"). SA-C is a C-like language that is partially suited for
compilation to hardware and has control structures to take advantage of
parallelism. The SA-C program is compiled into host code, and a dataflow graph.
The dataflow graph (DFG) is then translated into VHDL using a DFG - VHDL
translator. The host code and VHDL are then put onto the hardware (an FPGA) and
the process is complete.
Our 481 project for Robert Rinker will specifically target the DFG file. Certain
algorithms will produce "deep" dataflow graphs which will translate to
many gates and propagation delay in the hardware. Our task is to take these
sections of dataflow
graph data and generate a lookup table to replace them. This will have the
effect of increasing the speed of the calculation and eliminate the propagation
delay problem. Our plan is to use Lex and YACC with C/C++ to "compile"
these sections of DFG data
into the equivalent Lookup Table.
